This invention relates to an elastic store for use in data transfer in a time division multiple communication network.
In such a time division multiple communication network, a data transmitting device and a data receiving device are supplied with a sequence of system clock pulses having a system clock phase and a predetermined clock period and a sequence of system frame pulses comprising successive frames each of which has a system frame phase and a predetermined frame period defining a frame length. The data transmitting device transmits transmission data together with transmission clock pulses synchronized with the system clock pulses and transmission frame pulses synchronized with the system frame pulses to the data receiving device through a time division transmission path. The data receiving device receives the transmission data, the transmission clock pulses, and the transmission frame pulses as a sequence of reception data, a sequence of reception clock pulses, and a sequence of reception frame pulses, respectively. The reception clock pulses have a clock phase deviated from the system clock phase. The reception frame pulses have a frame phase deviated from the system frame phase. These phase deviations are caused by the time division transmission path.
The data receiving device comprises an elastic store supplied with the reception data, the reception clock pulses, the reception frame pulses, the system clock pulses, and the system frame pulses. The elastic store is for producing output data synchronized with the system frame phase within a predetermined phase difference. The elastic store has a data memory block comprising a data memory, a write-in counter, and a read-out counter. The write-in counter is reset by each of the reception frame pulses and generates a write-in address signal to supply the write-in address signal to the data memory. In synchronism with the reception clock pulses, the data memory memorizes the reception data, as memorized data, from a leading address to a trailing address in ascending order in accordance with the write-in address signal. The read-out counter is reset by each of the system frame pulses and generates a read-out address signal to supply the read-out address signal to the data memory. In synchronism with the system clock pulses, the memorized data are read out of the data memory in accordance with the read-out address signal.
Inasmuch as the above-mentioned elastic store has a single data memory block, the memorized data stored in a certain address of the data memory are held during a predetermined period. In other words, it is impossible to write the reception data at the certain address until the memorized data stored in the certain address are read out of the data memory. For the reason, it is required that the data memory has a capacity larger than the frame length or has a capacity equal to 1/N of the frame length where N represents a positive integer greater than unity.
However, it is hard for the elastic store to have the data memory of a large capacity because a quantity of the transmission data per frame shows a tendency to increase as a transmission rate becomes high. If the capacity of the data memory is reduced, the capacity is restricted to 1/N of the frame length. In other words, a write-in period of the write-in counter and a read-out period of the read-out counter are restricted to 1/N of the frame length. If the data memory has the capacity which is not coincide with 1/N of the frame length, miss read-out operation may occur. For example, when last or trailing data in a certain frame are memorized at the leading address of the data memory, the trailing data are held no more than the predetermined clock period. In this event, when the read-out counter generates the read-out address signal representative of the leading address, content of the leading address in the data memory has already been rewritten from the trailing data of the certain frame to new data of a next frame. This means that the trailing data of the certain frame can not be read out of the data memory.